Translation Lookaside Buffers (TLB)

Due to their size, page tables are typically maintained in memory in paging techniques. 

This design could have a significant effect on performance. Take an instruction that duplicates one register to another, for instance. This instruction only uses one memory reference to fetch the instruction when paging is not present. 

To access the page table when using paging, additional memory references will be required. Making two page table references for every memory reference affects performance by two-thirds because the rate at which the CPU can get instructions and data from memory largely determines how quickly an application can run. No one would utilize it in this scenario.

This issue has been well-known to computer designers for a long time, and they have developed a remedy. Their technique is based on the observation that, rather than the other way around, most programs prefer to make several references to a limited number of pages. As a result, only a tiny percentage of the page table items are heavily read, while the remainder are hardly ever used.

A small hardware component for mapping virtual addresses to physical addresses without using the page table has been added to computers as a solution. 

The following Figure shows the device, often known as a TLB (Translation Lookaside Buffer) or occasionally an associative memory. 

It typically has eight entries, for example, and is found inside the MMU. 

Rarely does it have more than 64 entries. 

The virtual page number, a bit that is set when a page is edited, the protection code (read/write/execute rights), and the physical page frame that the page is situated are all included in each entry. These fields correspond exactly in every way to the fields in the page table.

Happy Exploring!